SRFF

Problem #139

Tags: logic

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Now let's take a look at something a bit different - the Set-Reset Flip-Flop.

     ┌────────────┐        
 S ●─┤            ├─● Q    
     │    SRFF    │        
 R ●─┤            ├─● QBAR 
     └────────────┘        

This chip is different than the others we've looked at so far.
The SRFF has two input pins Set S and Reset R, and two output pins Q and QBAR.
Receiving a 1 signal on S will set Q to 1, until R receives a 1.
Receiving a 1 signal on R will reset Q to 0, until S receives a 1.
QBAR will always transmit the opposite signal of Q.

So the chip has some internal "memory" of which input was the last received.
There's another detail - the chip isn't constantly checking to see if the S or R pins are 1, but rather only applies the Set or Reset functions on the Rising Edge of the signal.
The rising edge is the instant where the signal turns from low to high, whereas the falling edge is the instant where the signal turns from low to high. Let's visualize the pin states through time.

    ║               ┌────┐    ┌────┐                        ┌─────────┐ ┌────────────────┐    
   S║               │    │    │    │                        │         │ │                │    
    ║───────────────┘    └────┘    └────────────────────────┘         └─┘                └────
                    ^         ^                             ^           ^                     
----------------------------------------------------------------------------------------------

    ║     ┌────┐                        ┌────┐    ┌────┐         ┌───────────┐ ┌────┐         
   R║     │    │                        │    │    │    │         │           │ │    │         
    ║─────┘    └────────────────────────┘    └────┘    └─────────┘           └─┘    └─────────
          ^                             ^         ^              ^             ^              
==============================================================================================

    ║─────┐         ┌───────────────────┐                   ┌────┐      ┌──────┐              
   Q║     │         │                   │                   │    │      │      │              
    ║     └─────────┘                   └───────────────────┘    └──────┘      └──────────────

----------------------------------------------------------------------------------------------

    ║     ┌─────────┐                   ┌───────────────────┐    ┌──────┐      ┌──────────────
QBAR║     │         │                   │                   │    │      │      │              
    ║─────┘         └───────────────────┘                   └────┘      └──────┘              

The rising edges of S and R are marked with a ^. Notice how Q and QBAR only respond to the rising edges.

In a traditional Set-Reset Flip-Flop, there are two issues: A) when the simulation begins the state of Q is random, and B) when both S and R read a rising edge simultaneously, the state of Q is undefined.
For our RSL chip, let's define that A) when the simulation begins the state of Q is 1, and B) when both S and R read a rising edge simultaneously, the output is random (this case will not be tested).

The circuit board will come pre-installed with INPUT and OUTPUT chips as shown below:

───────┐                                                   ┌────────
       ├─● S                                           Q ●─┤        
 INPUT │                                                   │ OUTPUT 
       ├─● R                                        QBAR ●─┤        
───────┘                                                   └────────

Problem Statement

Real-Time Testcases
This task is the first to use the "real-time" alternative of testing. See the Wiki Page for a detailed explanation.

Digital Logic Circuit Interface
For these Digital Logic Circuits tasks, you will not be providing an answer string you would for other tasks.
Instead, your Solution Code will be interpreted directly to place chips onto the circuitboard and connect them with wires.
Click here to learn the Digital Logic Circuit Syntax used on this site.

After the chips have been placed and connected, the server will run a series of tests, randomly assigning values to the input pin(s) and checking to see if the output pins read the corresponding expected values. If all tests produce the expected outputs, then the circuitboard is considered a success.

Even though we won't be using the "Your answer" box, you'll still need to put something in that box to submit your solution. Just put anything - it will not be passed to the interpreter.

Additional Info
The following information isn't critical to solving the task, but may still be useful.
In real life, the term Flip-Flop is used when a chip like this only operates on the rising edge of a clock cycle, supplied by some external chip with a regularly oscillating signal. A chip which is timed according to a clock signal is called a synchronous chip. If no clock signal is used and the changes happen instantaneously, then the chip is usually referred to as a Latch instead, being asynchronous.
For the tasks on this website, we won't worry too much about syncing things up with a clock signal. Or maybe we can call each 'tick' a clock cycle. Either way, we will refer to all of these types of chips as Flip-Flops on this site.

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