Here's a more detailed explanation of how the server simulates circuitboards.
(Click here to view instructions on Digital Logic Circuit Syntax)
After all of the declared chips and wires have been virtually placed onto the circuitboard, the server will simulate the relaying of signals through the circuitboard in discrete steps called ticks. During each tick, the following two steps occur:
Note that these two steps happen in that exact order. First all chips are processed, then each wire is processed. Because of this, it often takes a few ticks for the circuit to "settle" until all wire states remain constant.
Let's look at an example - take a circuitboard with a single INPUT, two NOT chips, and single OUTPUT, all wired together in a line.
TICK: 0
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─● ------- ●─┤ NOT2 ├─● ------- ●─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
Since the incoming signal is inverted, then inverted again, we would expect that state of INPUT and OUTPUT to match.
INPUT.OUT ║ OUTPUT.IN
───────────║───────────
0 ║ 0
1 ║ 1
However, let's take a look tick-by-tick to see what actually happens, using a + sign to indicate a powered wire or pin, and keeping - or ● to represent unpowered.
At the first half of the tick, each chip reads its input pins and configures its output pins accordingly. Let's leave the input pin unpowered for now.
TICK: 1-A
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ ------- ●─┤ NOT2 ├─+ ------- ●─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
Each NOT chip notices that its input pin is unpowered, and so it powers its output pin. In the second half of the tick, each wire becomes powered or unpowered according to its connection.
TICK: 1-B
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ +++++++ ●─┤ NOT2 ├─+ +++++++ ●─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
The above is the final state for the first tick, and we can see that the OUTPUT is reading as unpowered, matching the state of the INPUT, but let us observe it for another tick.
TICK: 2-A
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ +++++++ +─┤ NOT2 ├─● +++++++ +─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
Uh oh - the OUTPUT is reading as powered now! Both the OUTPUT and the NOT2 chips have adjusted their states based on their preceding wires. Then the wires get updated...
TICK: 2-B
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ +++++++ +─┤ NOT2 ├─● ------- +─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
Let's continue to let the circuit settle...
TICK: 3-A
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ +++++++ +─┤ NOT2 ├─● ------- ●─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
TICK: 3-B (no change)
───────┐ ┌──────────┐ ┌──────────┐ ┌────────
│ │ │ │ │ │
INPUT ├─● ------- ●─┤ NOT1 ├─+ +++++++ +─┤ NOT2 ├─● ------- ●─┤ OUTPUT
│ │ │ │ │ │
───────┘ └──────────┘ └──────────┘ └────────
And now we see that all pins and the wires to which they are connected now match their states, and so the system has "settled" after 3 ticks.
Most tasks will be simulated by setting the INPUT pins to some configuration, allowing the circuitboard to settle for about 100 ticks, then reading the OUTPUT pins and verifying if they match the expected values from the associated truth table. Note that the server does not actually check if a circuitboard has settled or not before verifying to the truth table.
Before each testcase the circuitboard will be completely de-powered, so that each testcase has a "clean" start.
Certain tasks (especially later ones) use an alternative method, continuously changing and reading pins in real time, then comparing the measured outputs to the expected, yielding an overall matched percentage score. Pins will be toggled on and off semi-randomly.
For example, let's take our above circuitboard. Here's a table describing the states at each pin at each tick.
TICK ║ INPUT.OUT ║ OUTPUT.IN ║ OUTPUT.IN ║ MATCH
║ ║ (ACT) ║ (EXP) ║
──────║───────────║───────────║───────────║───────
1 ║ 0 ║ 0 ║ 0 ║ Y
2 ║ 0 ║ 1 ║ 0 ║ N
3 ║ 0 ║ 0 ║ 0 ║ Y
4 ║ 0 ║ 0 ║ 0 ║ Y
5 ║ 0 ║ 0 ║ 0 ║ Y
6 ║ 1 ║ 0 ║ 1 ║ N
7 ║ 1 ║ 0 ║ 1 ║ N
8 ║ 1 ║ 0 ║ 1 ║ N
9 ║ 1 ║ 1 ║ 1 ║ Y
10 ║ 1 ║ 1 ║ 1 ║ Y
After starting from a fully-unpowered state in tick 0, the INPUT pin is held low for 5 ticks, then held high for 5 ticks. We see that due to the delay caused by the signal propogating across the chips and wires, we can see that the actual output only matches the expected output for 60% of the ticks.
To be considered passing, the circuitboard must match the expected values at least 95% of the time. However note that if the INPUT pin in the above problem had changed state every 10 ticks indead of every 5 ticks, then after the 20th total tick it would have matched 80% of the time.
TICK ║ INPUT.OUT ║ OUTPUT.IN ║ OUTPUT.IN ║ MATCH
║ ║ (ACT) ║ (EXP) ║
──────║───────────║───────────║───────────║───────
1 ║ 0 ║ 0 ║ 0 ║ Y
2 ║ 0 ║ 1 ║ 0 ║ N
3 ║ 0 ║ 0 ║ 0 ║ Y
4 ║ 0 ║ 0 ║ 0 ║ Y
5 ║ 0 ║ 0 ║ 0 ║ Y
6 ║ 0 ║ 0 ║ 0 ║ Y
7 ║ 0 ║ 0 ║ 0 ║ Y
8 ║ 0 ║ 0 ║ 0 ║ Y
9 ║ 0 ║ 0 ║ 0 ║ Y
10 ║ 0 ║ 0 ║ 0 ║ Y
11 ║ 1 ║ 0 ║ 1 ║ N
12 ║ 1 ║ 0 ║ 1 ║ N
13 ║ 1 ║ 0 ║ 1 ║ N
14 ║ 1 ║ 1 ║ 1 ║ Y
15 ║ 1 ║ 1 ║ 1 ║ Y
16 ║ 1 ║ 1 ║ 1 ║ Y
17 ║ 1 ║ 1 ║ 1 ║ Y
18 ║ 1 ║ 1 ║ 1 ║ Y
19 ║ 1 ║ 1 ║ 1 ║ Y
20 ║ 1 ║ 1 ║ 1 ║ Y
In actual tasks the exact timing of input toggling will be pseudo-randomized in each test, so any given circuitboard may differ slightly in performance from test to test.
To see a visual of the expected and measured Input/Output pinstates of your board during the simulation, include the comment #VISUAL by itself on any instruction line.